In an effort to increase the performance and speed of semiconductor devices, semiconductor device manufacturers have sought to reduce the linewidth and spacing of interconnects while minimizing the transmission losses and reducing the capacitative coupling of the interconnects. One way to diminish power consumption and reduce capacitance is to decrease the dielectric constant (also referred to as “k”) of the insulating material, or dielectric, that separates the interconnects. Insulator materials having low dielectric constants are especially desirable, because they typically allow faster signal propagation, reduce capacitance and cross talk between conductor lines, and lower voltages required for driving integrated circuits. Therefore, as interconnect linewidths decrease, concomitant decreases in the dielectric constant of the insulating material are required to achieve the improved performance and speed desired of future semiconductor devices. For example, devices having interconnect linewidths of 0.13 or 0.10 micron and below seek an insulating material having a dielectric constant (k)<3. Semiconductor device manufacturers also seek materials that in addition to having a low dielectric constant, have the mechanical and thermal stability needed to withstand the thermal cycling and processing steps of semiconductor device manufacturing.
In a typical damascene process, a line pattern is etched in the surface of a insulating material, and the trenches formed in this manner, i.e., the horizontal structure created to house the horizontal electrical connections within a particular level or layer in a semiconductor device, is filled with copper by electroplating, electroless plating, or sputtering. After the copper is deposited onto the entire surface, a chemical-mechanical planarization (CMP) step is employed to remove excess copper, and to planarize the wafer for subsequent processing steps. This process is typically repeated several times to form vias, i.e., the vertical structures created to contain the vertical electrical connections that connect the trenches between at least two metal levels or layers of metal in a semiconductor device.
To further improve the damascene process, via and line formation can be integrated into a single process, which is then called dual damascene process. In the dual damascene process, a via dielectric layer is laid down onto a substrate, and the via dielectric layer is subsequently coated with a patterned etch stop layer, i.e., a layer that controls the etching or removal of the dielectric, whereby voids in the etch stop layer correspond to positions of vias that will be etched into the via dielectric. In a next step, a line dielectric is deposited onto the etch stop layer, which in turn is coated with a patterned hardmask layer that defines the traces of the lines. Current hardmask layers are made of silicon nitride, silicon oxynitride, silicon oxide, or silicon carbide. In a following step via and line traces are formed, whereby the line trenches are etched into the line dielectric until the etchant reaches the etch stop layer. In positions where there is no etch stop layer, the etching process continues through the via dielectric to form a via. As in the damascene process, etched via and line traces are filled with copper (after applying a Ta(N) barrier layer and a Cu-seed layer) and a CMP step finishes the dual damascene process.
Dielectric etching is difficult to control with today's required trench width of 0.13 micron. Thus, the etch stop performs a critical role in semiconductor device construction. A disadvantage of known hardmask and etch stop materials is their relatively high dielectric constant (k-value). For example, typical hardmask and etch stop materials, including SiN, SiON, SiO2, and SiC, have an undesirably high dielectric constant of at least about 4.0 and are applied by chemical vapor deposition (CVD). Although J. J. Waeterloos et al., “Integration of a Low Permittivity Spin-on Embedded Hardmask for Cu/SiLK Resin Dual Damascene”, Proceedings of the IEEE 2001 International Interconnect Technology Conference, pages 60-62 (Jun. 4-6, 2001) teaches that a low-k spin-on organosiloxane film may replace the preceding known etch stop materials to lower the effective k value, the article reports that the organosiloxane film has a k value of 3.2 and does not disclose any details about the organosiloxane used.
U.S. Pat. No. 4,626,556 teaches organosilsesquioxane having required alkyl and alkenyl group side chains bonded thereto and optionally aryl groups and hydrogen side chains bonded thereto as a substitute for a photoresist material. U.S. Pat. No. 4,626,556 does not teach that its organosilsesquioxane may function as an etch stop or hardmask. In Comparative A below, we made an organosilsesquioxane having the required minimum at least 50% methyl groups of U.S. Pat. No. 4,626,556 and this material did not wet known dielectric materials and thus, would not be useful as an etch stop. Although U.S. Pat. No. 4,626,556 teaches that its organosilsesquioxane films have low dielectric constants, U.S. Pat. No. 4,626,556 does not report any dielectric constant values. However, as those skilled in the art know, silanol results in an undesirable dielectric constant and U.S. Pat. No. 4,626,556's organosilsesquioxane transmission FTIR plots show that silanol (3400-3700/cm) is present. Also, U.S. Pat. No. 4,626,556 teaches in a preferred embodiment, the presence of a crosslinking agent that is light activated and as those skilled in the art know, that these materials have high dielectric constants. Also, U.S. Pat. No. 4,626,556 teaches that at least 50% of its side chains are alkyl groups since the larger the amount of the alkyl group present, the higher the heat resistance U.S. Pat. No. 4,626,556's Examples 13 and 14 teach that its organosilsesquioxane was applied to a two inch thick silicone wafer wherein a thin film of one micron was formed; the film was then heated at 250° C. for 2 hours, at 350° C. for 1 hour, and then at 450° C. for 30 minutes, and subjected to thermogravimetric analysis, in which no weight loss was observed up to 600° C. It is not clear if the silicone wafer weight was included in the “no weight loss” reported. Today's semiconductor manufacturers require a more stringent TGA test of a film alone and not on a wafer. This current more stringent TGA test requires heating and holding at 200° C. (Weight loss represents how well the material was dried.), holding at 430° C. for 90 minutes (Weight loss represents worst case scenario for shrinkage from low temperature bake to high temperature cure.), and heating at 450° C. (Weight loss represents thermal stability.). Thus, U.S. Pat. No. 4,626,556's organosilsesquioxane does not have the wetting characteristics, low dielectric constant, and thermal stability required by today's semiconductor manufacturers.
In 1999, AlliedSignal Inc., now Honeywell International Inc., introduced HOSP® product comprising organosiloxane having about 80% methyl groups and 20% hydrogen groups. US Patent Publication 2001/006848A1 published Jul. 5, 2001 teaches that AlliedSignal's HOSP™ product is useful as a hardmask. Unfortunately, as reported in Comparative A below, this product does not have acceptable wetting properties with organic dielectrics.
Commonly assigned U.S. Pat. Nos. 5,973,095; 6,020,410; 6,043,330; 6,177,143; and 6,287,477 teach organohydridosiloxane resins of the formula (H0.4-1.0SiO1.5-1.8)n(R0.4-1.0SiO1.5-1.8)m where R is alkyl groups, aryl groups, and mixtures thereof. See also commonly assigned U.S. Pat. No. 6,015,457. Unfortunately, as reported in Comparative B below, a composition comprising 50% phenyl groups and 50% hydrogen subjected to the current stringent TGA test had a weight loss of 1.0 percent per hour.
Thus, a need still exists in the semiconductor industry to provide: a) compositions with lower dielectric constants; b) compositions with improved mechanical properties, such as thermal stability, glass transition temperature (Tg), and hardness; c) compositions that are capable of being solvated and spun-on to a wafer or layered material; and d) compositions that are versatile enough to function as a hardmask or an etch stop and can wet dielectric materials.